High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking chips (e.g., dies) vertically and interconnecting the chips using through substrate vias (TSVs). Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM), and a wide-I/O dynamic random access memory (DRAM).
For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance DRAM interface chip and vertically stacked DRAM chips. A typical HBM stack of four DRAM chips (e.g., core chips) has two 128-bit channels per chip for a total of eight input/output channels and a width of 1024 bits in total. An interface (IF) chip of the HBM provides an interface with the eight input/output channels, which function independently of each other. In the HBM, data transmission between chips (e.g., between an interface chip and core chips) via through substrate vias (TSVs) may cause high power consumption, due to current charge and discharge at the TSVs as capacitors.
3D memory devices (e.g., HBM and the like) support data bus inversion (“DBI”) during write and read operation for reducing currents in data transmission between a host controller and chips (e.g., dies) via a data bus. One of DBI algorithms, DBI-AC algorithm, is used to limit the number of simultaneously transitioning data bits (e.g., a half of bits or fewer) across the width of the interface. Under the DBI-AC algorithm, all the bits of current data to be transmitted are inverted in logic level prior to transmission of the current data, if a majority of bits of the current data are different in logic level from previous data (e.g., immediately preceding data) transmitted one data transmission cycle before the current data without inversion. If the previous data was transmitted with inversion, however, the current data is transmitted as is, even if the majority of bits of the current data are different in logic level from the previous data.
DBI calculation is performed to detect whether the majority bits of the current data are different in logic level from the previous data. Based on the majority bits' transitions based on the DBI calculation result and previous execution status of the DBI operation, a DBI bit indicating whether the DBI is executed on the current data. In FIG. 1A, the DBI bit represents “1,” if the majority bits of the current data are different in logic level from the previous data and the DBI was not executed on the previous data, and the DBI bit represents “0” if the majority of the bits of the current data are the same in logic level from the previous data. As shown in FIG. 1B, a DBI circuit 1 for data read path executes the DBI-AC algorithm and provides the current data with or without DBI and a DBI bit onto data bus. A data bus transmits each data from DRAM core in synchronous to a read clock signal READ. In response to each cycle of the read clock signal READ, a D-type flip-flop circuit 11 captures a data (DQ) and a DBI bit and provides the captured data (DQ) as previous data which with one cycle delay and the DBI bit and to a DBI calculator 12 that is a comparator. The DBI calculator 12 receives the current data from the DRAM core and the previous data that is the data one cycle before the current data from the flip-flop circuit 11. The DBI calculator 12 compares the previous data and the current data to determine whether a majority of bits in the data are different in logic level from the previous data (e.g., the number of bits showing difference is greater than four bits, if the width of the data bus is eight bits), and provides a DBI calculation result bit to a logic AND circuit 13. The logic AND circuit 13 receives the DBI calculation result and a DBI enable/disable bit from a mode register and provides the DBI bit to a logic XOR circuit 14. The DBI bit is active (e.g., “1”) when both the DBI calculation result is indicative of the majority of bits in the current data being different from the previous data and the DBI enable/disable bit is indicative of the DBI operation enabled. The logic XOR circuit 14 executes inversion of the current data if the DBI bit is active (e.g., “1”), thus the DBI circuit 1 provides a combination of the inverted current data DQ and the DBI bit “1,” or a combination of the current data DQ and the DBI bit “0.” The DBI calculation is supposed to be executed within one cycle of the read clock signal READ; however, completion of DBI calculation takes relative long time because the DBI calculator 12 is composed of a large number of logic gates. Thus, a cycle of the read clock signal READ has been required to be sufficiently long to complete the DBI computation, and thus a data transfer speed with the DBI operations has been suppressed.